The fabrication of integrated circuit chips has become a sophisticated process that can allow complex circuitry to be densely packaged onto a single wafer, also known as a substrate. Originally, most chips were fabricated in a simple planar design. As the need for greater density of circuitry on a single substrate grew, the early simple planar chip designs proved inadequate. Indeed, the planar designs limited the amount of circuitry that could be placed on a single substrate, and further limited the implementation of multi-technology circuits such as Si CMOS and SiGe, or integrated device circuits such as a MEMS device and a related control circuit.
To overcome some of the limitations resulting from the planar design, designers began stacking chips to form three-dimensional designs. Vias extending through the wafer create three-dimensional interconnects which facilitate connection to the circuitry throughout the chip, thereby allowing the implementation of more advanced circuits and device architectures, and increasing the computing capacity of the chip. For example, three-dimensional designs increase the physical space available on the chip, thereby allowing a higher density of complex circuitry to be placed within a given die area. Furthermore, a three-dimensional design with through-wafer vias can enable advanced micro-electronic chip stacking or the stacking of various types of micro-components directly onto the chip. Multiple components on a single chip allow, for example, increased processing of image data and signal processing.
Although three-dimensional chips using through-wafer vias have proven useful, they are currently limited. In one approach, through-wafer vias have been formed in thick substrates. At thicknesses in excess of 200-400 microns, the wafers retain mechanical durability and can be easily handled and processed without the need for sequential stacking and thinning operations. In the thick wafer approach, wafers are etched and the formed vias are electrically insulated and metalized. Once the vias have been formed and metalized, the three-dimensional circuits are assembled by stacking (either at wafer-level or die-level).
Although this approach provides some advantages, for example, the ability to process the circuit layers in parallel, test for functionality, and assemble the 3D stack in an efficient manner, and addresses the mechanical integrity of the wafer, it introduces other limitations. In particular, one limitation is the inability to fabricate small-diameter, fine-pitch vias. Indeed, due to current etching techniques, the formation of high-aspect ratio (ratio of depth to diameter) vias results in a large diameter-to-pitch (pitch is the center to center measurement between vias) ratio for the vias. This limits the etch depth of the vias, and also reduces the amount of available space on the wafer for other uses. Current techniques typically produce vias having diameters of about 4 μm with a depth of about 20 μm (low temperature techniques) and 100 μm diameters with a depth of about 500 μm (high temperatures techniques), rendering an aspect ratio of about 1:5 for both high temperature and low temperature techniques. Both dry etching and wet etching have been demonstrated for the thick wafer processing, and both suffer from constraints on via size and separation. In addition, it is very difficult to reliably deposit electrical isolation layers and metallic conductors using low process temperature in the high aspect ratio vias. In current systems the larger diameter vias are tolerated as ensuring the deposition of conformal isolation and conductive layers becomes increasingly difficult with smaller diameter vias.
To reduce the vias diameters, some techniques stack, bond and thin multiple wafers into a ‘single’ wafer and form the vias through only a single thin layer of the stacked wafers at a time, thereby reducing the aspect ratio and diameter required of an individual via. This approach involves wafer thinning to reduce the required etch depth, and hence enable smaller via diameters to be achieved. In this approach, two wafers to be stacked are bonded and one portion (top or bottom) of the stacked wafers is thinned. The thinning requires a significantly reduced thickness of the wafer (typically 10-25 μm). At this thickness, vias can be etched through the thinned layer while maintaining small diameter and small separation between neighboring vias. Alternatively, the via could be etched to a limited depth prior to the bonding, and then its bottom surface exposed in the thinning operation after bonding. In either process, the reduced layer thickness is necessary due to the aspect ratio limitations of the etch process. The advantages of this approach include the ability to use well-developed fabrication processes. However, disadvantages arise from the need for sequential processing of each successive layer and the complexity of intermediate testing. Further, although this allows for via depth greater than one wafer, the thinning of the stacked wafers reduces their integrity and makes them more susceptible to breakage during use and damage from handling. Further still, many current bonding techniques involve high temperatures, high voltage and/or high pressure. Each of these poses difficulties if the stacking includes prefabricated integrated circuits with multi-level interconnects as the process could damage the circuitry.
Furthermore, many current via fabrication techniques, such as thermal oxidation and polysilicon deposition, are performed at high temperatures because conformal depositions, such as the insulation or conductive layers, require higher temperatures for successful deposition into the vias. However, these higher temperature processes cannot be used for circuit wafers, such as CMOS, as the higher temperatures can damage or destroy the circuitry. Rather, these techniques are generally limited to microelectromechanical system (“MEMS”) applications without integrated circuitry. For circuitry applications, to use low temperature techniques such as electroplating with thin wafers, the vias must normally have large diameters to achieve uniform internal coverage by insulating or conductive layers, small diameter vias require thinning the wafers.
A need exists in the industry to fabricate high aspect ratio, small diameter through-wafer vias in relatively thick substrates to enable parallel layer processing, known-good-die testing, and either die-level or wafer-level assembly. A further need exists in the industry for fabricating through-wafer, small diameter vias at low temperatures. A still further need exists for a process to uniformly coat small diameters vias.